IMX8MPCEC datasheet(75/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Figure 42. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

NOTE

Timing shown is based on the memory generating read data on the SCK

falling edge and read strobe on the SCK rising edge. The FlexSPI controller

samples read data on a half-cycle delayed DQS falling edge.

3.8.12.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2

Table 59. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation

—

166

MHz

[D:] Time from SCK to data valid

—

[D:] Time from SCK to DQS

—

[D:] Time delta between TSCKD and

TSCKDQS

-2

Table 60. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol

Parameter

Min.

Max.

Unit

Notes

—

[D:] Frequency of operation

—

MHz

—

[D:] Setup time for incoming data

8.67

—

1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be

decreased by up to 2ns.

[D:] Hold time for incoming data

—

Table 61. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2

Symbol

Parameter

Min.

Max.

Unit

Notes

—

[D:] Frequency of operation

—

MHz

—

[D:] Setup time for incoming data

1.5

—

1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be

decreased by up to 2ns.

[D:] Hold time for incoming data

—

FLEXSPI_SCLK

FLEXSPI_DATA[7:0]

FLEXSPI_DQS

Internal Sample Clock

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