IMX8MPCEC datasheet(76/111 Pages) NXP

76 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

Figure 43. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2

3.8.12.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

Figure 44. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3

3.8.12.2 FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals

and data outputs.

3.8.12.2.1 SDR mode

Table 62. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case 1)

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation

—

166

MHz

TSCKD

[D:] Time from SCK to data valid

—

TSCKDQS

[D:] Time from SCK to DQS

—

TSCKD - TSCKDQS

[D:] Time delta between TSCKD and

TSCKDQS

-0.6

0.6

Table 63. FlexSPI output timing in SDR mode

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation1

—166

MHz

TCK

[D:] SCK clock period

6.02

—

F1 F2

SCLK

SIO[0:7]

Internal Sample Clocks

TSCKD

TSCKDQS

SCK

SIO[0:7]

DQS

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