IMX8MPCEC datasheet(50/111 Pages) NXP

50 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

3.8.2.3

HS400 DDR AC timing

Figure 17 depicts the timing of HS400 mode, and Table 41 lists the HS400 timing characteristics. Be

aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD

input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check

SD5, SD6, and SD7 parameters in Table 43 SDR50/SDR104 Interface Timing Specification for CMD

input/output timing for HS400 mode.

Figure 17. HS400 timing

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

uSDHC Output Delay

tOD

2.7

6.9

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD3

uSDHC Input Setup Time

tISU

2.4

—

SD4

uSDHC Input Hold Time

tIH

1.3

—

Table 41. HS400 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock frequency

fPP

200

MHz

SD2

Clock low time

tCL

0.46 x tCLK

0.54 x tCLK

SD3

Clock high time

tCH

0.46 x tCLK

0.54 x tCLK

uSDHC Output/Card Inputs DAT (Reference to SCK)

Table 40. eMMC5.1/SD3.0 (DDR) interface timing specification (continued)

Parameter

Symbols

Min

Max

Unit

SD7

SD1

SD5

SD6

SCK

Output from

Strobe

Input from

uSDHC to eMMC

eMMC to uSDHC

DAT0

DAT1

DAT7

...

DAT0

DAT1

DAT7

...

SD4

SD3

SD2

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