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IMX8MPCEC Datasheet(PDF) 54 Page - NXP Semiconductors |
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IMX8MPCEC Datasheet(HTML) 54 Page - NXP Semiconductors |
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54 / 111 page  i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021 54 NXP Semiconductors Electrical characteristics SAI1_TXFS RMII.RX_EN (CRS_DV); enet1.RGMII_RX_CTL RMII/RGMII ALT4 I — SAI1_TXC enet1.RGMII_RXC RGMII ALT4 I — SAI1_TXD0 enet1.RGMII_TD0 RMII/RGMII ALT4 O — SAI1_TXD1 enet1.RGMII_TD1 RMII/RGMII ALT4 O — SAI1_TXD2 enet1.RGMII_TD2 RGMII ALT4 O Only used for RGMII SAI1_TXD3 enet1.RGMII_TD3 RGMII ALT4 O Only used for RGMII SAI1_TXD4 RMII.TX_EN; enet1.RGMII_TX_CTL RMII/RGMII ALT4 O For RMII—SAI1_TXD4 works as RMII.TX_EN. For RGMII—SAI1_TXD4 works as enet1.RGMII_TX_CTL. SAI1_TXD5 enet1.RGMII_TXC RGMII ALT4 O — SAI1_TXD6 enet1.RX_ER RMII ALT4 I — SAI1_TXD7 enet1.TX_ER RMII ALT4 O — SAI1_MCLK enet1.RMII_CLK RMII ALT4 I/O Used as RMII clock, there are two RMII clock schemes: • MAC generates output 50M reference clock for PHY, also MAC uses this 50M clock. • MAC uses external 50M clock. SD1_CLK enet1.MDC RMII ALT1 O — SD1_CMD enet1.MDIO RMII ALT1 I/O — SD1_DATA0 enet1.RGMII_TD1 RMII ALT1 O — SD1_DATA1 enet1.RGMII_TD0 RMII ALT1 O — SD1_DATA2 enet1.RGMII_RD0 RMII ALT1 I — SD1_DATA3 enet1.RGMII_RD1 RMII ALT1 I — SD1_DATA4 RMII.TX_EN RMII ALT1 O — SD1_DATA5 enet1.TX_ER RMII ALT1 O — SD1_DATA6 RMII.RX_EN (CRS_DV) RMII ALT1 I — SD1_DATA7 enet1.RX_ER RMII ALT1 I — SD1_RESET_B enet1.RMII_CLK RMII ALT1 I/O Used as RMII clock, there are two RMII clock schemes: • MAC generates output 50M reference clock for PHY, also MAC uses this 50M clock. • MAC uses external 50M clock Table 44. ENET1 signal mapping (continued) (Sheet 2 of 2) Pad name Description Mode Alt mode Direction Comments |
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