MPC850 datasheet(18/72 Pages) FREESCALE

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MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Bus Signal Timing

B42

CLKOUT rising edge to TS valid

(hold time)

2.00

—

2.00

—

2.00

—

50.00

B43

AS negation to memory

controller signals negation

—TBD

TBD

—

50.00

The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on

the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC

parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to

be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the

part. The following equations should be used in these calculations.

For a frequency F, the following equations should be applied to each one of the above parameters:

For minima:

For maxima:

where:

D is the parameter value to the frequency required in ns

F is the operation frequency in MHz

D50 is the parameter value defined for 50 MHz

CAP LOAD is the capacitance load on the signal in question.

FFACTOR is the one defined for each of the parameters in the table.

Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.

If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum

values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then

the maximum allowed jitter on EXTAL can be up to 2%.

The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for

BG output is relevant when the MPC850 is selected to work with internal bus arbiter.

The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and

not when the memory controller or the PCMCIA interface drives them).

The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The

timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter.

The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input

signal is asserted.

The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for

read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3

= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.

The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.

10 The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in

B37 and B38 are specified to enable the freeze of the UPM output signals.

11 The AS signal is considered asynchronous to CLKOUT.

Table 6. Bus Operation Timing 1 (continued)

Num

Characteristic

50 MHz

66 MHz

80 MHz

FFACT

Cap Load

(default

50 pF)

Unit

Min

Max

Min

Max

Min

Max

D =

FFACTOR x 1000

(D50 - 20 x FFACTOR)

D =

FFACTOR x 1000

(D50 -20 x FFACTOR)

1ns(CAP LOAD - 50) / 10

MPC850 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

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