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MPC850 Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc |
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MPC850 Datasheet(HTML) 17 Page - Freescale Semiconductor, Inc |
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17 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 17 Bus Signal Timing B33a CLKOUT rising edge to GPL valid - as requested by control bit GxT3 in the corresponding word in the UPM 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns B34 A[6–31] and D[0–31] to CS valid - as requested by control bit CST4 in the corresponding word in the UPM 3.00 — 6.00 — 4.00 — 0.250 50.00 ns B34a A[6–31] and D[0–31] to CS valid - as requested by control bit CST1 in the corresponding word in the UPM 8.00 — 13.00 — 11.00 — 0.500 50.00 ns B34b A[6–31] and D[0–31] to CS valid - as requested by CST2 in the corresponding word in UPM 13.00 — 21.00 — 17.00 — 0.750 50.00 ns B35 A[6–31] to CS valid - as requested by control bit BST4 in the corresponding word in UPM 3.00 — 6.00 — 4.00 — 0.250 50.00 ns B35a A[6–31] and D[0–31] to BS valid - as requested by BST1 in the corresponding word in the UPM 8.00 — 13.00 — 11.00 — 0.500 50.00 ns B35b A[6–31] and D[0–31] to BS valid - as requested by control bit BST2 in the corresponding word in the UPM 13.00 — 21.00 — 17.00 — 0.750 50.00 ns B36 A[6–31] and D[0–31] to GPL valid - as requested by control bit GxT4 in the corresponding word in the UPM 3.00 — 6.00 — 4.00 — 0.250 50.00 ns B37 UPWAIT valid to CLKOUT falling edge 10 6.00 — 6.00 — 6.00 — — 50.00 ns B38 CLKOUT falling edge to UPWAIT valid 10 1.00 — 1.00 — 1.00 — — 50.00 ns B39 AS valid to CLKOUT rising edge 11 7.00 — 7.00 — 7.00 — — 50.00 ns B40 A[6–31], TSIZ[0–1], RD/WR, BURST, valid to CLKOUT rising edge. 7.00 — 7.00 — 7.00 — — 50.00 ns B41 TS valid to CLKOUT rising edge (setup time) 7.00 — 7.00 — 7.00 — — 50.00 ns Table 6. Bus Operation Timing 1 (continued) Num Characteristic 50 MHz 66 MHz 80 MHz FFACT Cap Load (default 50 pF) Unit Min Max Min Max Min Max |
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