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MPC850 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MPC850 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 11 Bus Signal Timing Table 6. Bus Operation Timing 1 Num Characteristic 50 MHz 66 MHz 80 MHz FFACT Cap Load (default 50 pF) Unit Min Max Min Max Min Max B1 CLKOUT period 20 — 30.30 — 25 — — — ns B1a EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz and MF <= 2) -0.90 0.90 -0.90 0.90 -0.90 0.90 — 50.00 ns B1b EXTCLK to CLKOUT phase skew (EXTCLK > 10 MHz and MF < 10) -2.30 2.30 -2.30 2.30 -2.30 2.30 — 50.00 ns B1c CLKOUT phase jitter (EXTCLK > 15 MHz and MF <= 2) 2 -0.60 0.60 -0.60 0.60 -0.60 0.60 — 50.00 ns B1d CLKOUT phase jitter 2 -2.00 2.00 -2.00 2.00 -2.00 2.00 — 50.00 ns B1e CLKOUT frequency jitter (MF < 10) 2 — 0.50 — 0.50 — 0.50 — 50.00 % B1f CLKOUT frequency jitter (10 < MF < 500) 2 — 2.00 — 2.00 — 2.00 — 50.00 % B1g CLKOUT frequency jitter (MF > 500) 2 — 3.00 — 3.00 — 3.00 — 50.00 % B1h Frequency jitter on EXTCLK 3 — 0.50 — 0.50 — 0.50 — 50.00 % B2 CLKOUT pulse width low 8.00 — 12.12 — 10.00 — — 50.00 ns B3 CLKOUT width high 8.00 — 12.12 — 10.00 — — 50.00 ns B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 50.00 ns B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 50.00 ns B7 CLKOUT to A[6–31], RD/WR, BURST, D[0–31], DP[0–3] invalid 5.00 — 7.58 — 6.25 — 0.250 50.00 ns B7a CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3], BDIP, PTR invalid 5.00 — 7.58 — 6.25 — 0.250 50.00 ns B7b CLKOUT to BR, BG, FRZ, VFLS[0–1], VF[0–2] IWP[0–2], LWP[0–1], STS invalid 4 5.00 — 7.58 — 6.25 — 0.250 50.00 ns B8 CLKOUT to A[6–31], RD/WR, BURST, D[0–31], DP[0–3] valid 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns B8a CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3] BDIP, PTR valid 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns B8b CLKOUT to BR, BG, VFLS[0–1], VF[0–2], IWP[0–2], FRZ, LWP[0–1], STS valid 4 5.00 11.74 7.58 14.33 6.25 13.00 0.250 50.00 ns |
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