MPC850 datasheet(62/72 Pages) FREESCALE

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MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

CPM Electrical Characteristics

Table 25 provides the I2C (SCL > 100 KHz) timings.

Figure 61 shows the I2C bus timing.

Figure 61. I2C Bus Timing Diagram

210

SDL/SCL fall time

—

300.00

211

Stop condition setup time

4.70

—

µs

SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.

Table 25. I2C Timing (SCL > 100 KHZ)

Num

Characteristic

Expression

All Frequencies

Unit

Min

Max

200

SCL clock frequency (slave)

fSCL

BRGCLK/48

200

SCL clock frequency (master) 1

SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.

fSCL

BRGCLK/16512

BRGCLK/48

202

Bus free time between transmissions

1/(2.2 * fSCL)

—

203

Low period of SCL

1/(2.2 * fSCL)

—

204

High period of SCL

1/(2.2 * fSCL)

—

205

Start condition setup time

1/(2.2 * fSCL)

—

206

Start condition hold time

1/(2.2 * fSCL)

—

207

Data hold time

—

208

Data setup time

1/(40 * fSCL)

—

209

SDL/SCL rise time

—

1/(10 * fSCL)

210

SDL/SCL fall time

—

1/(33 * fSCL)

211

Stop condition setup time

1/2(2.2 * fSCL)

—

Table 24. I2C Timing (SCL < 100 KHZ) (CONTINUED)

Num

Characteristic

All Frequencies

Unit

Min

Max

SCL

202

205

203

207

204

208

206

209

211

210

SDA

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