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MPC850 Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc |
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MPC850 Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 15 Bus Signal Timing B29h WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access TRLX = 0, CSNT = 1, EBDF = 1 25.00 — 39.00 — 31.00 — 1.375 50.00 ns B29i CS negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 25.00 — 39.00 — 31.00 — 1.375 50.00 ns B30 CS, WE[0–3] negated to A[6–31] invalid GPCM write access 9 3.00 — 6.00 — 4.00 — 0.250 50.00 ns B30a WE[0–3] negated to A[6–31] invalid GPCM write access, TRLX = 0, CSNT = 1, CS negated to A[6–31] invalid GPCM write access TRLX = 0, CSNT =1, ACS = 10 or ACS = 11, EBDF = 0 8.00 — 13.00 — 11.00 — 0.500 50.00 ns B30b WE[0–3] negated to A[6–31] invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A[6–31] Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 28.00 — 43.00 — 36.00 — 1.500 50.00 ns B30c WE[0–3] negated to A[6–31] invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A[6–31] invalid GPCM write access, TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 5.00 — 8.00 — 6.00 — 0.375 50.00 ns B30d WE[0–3] negated to A[6–31] invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A[6–31] invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 25.00 — 39.00 — 31.00 — 1.375 50.00 ns Table 6. Bus Operation Timing 1 (continued) Num Characteristic 50 MHz 66 MHz 80 MHz FFACT Cap Load (default 50 pF) Unit Min Max Min Max Min Max |
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