MPC850 datasheet(47/72 Pages) FREESCALE

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MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

CPM Electrical Characteristics

Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)

L1RCLK, L1TCLK frequency (DSC =1)

—

16.00 or

SYNCCLK/2

MHz

L1RCLK, L1TCLK width low (DSC =1)

P + 10

—

83A

L1RCLK, L1TCLK width high (DSC = 1)3

P + 10

—

L1CLK edge to L1CLKO valid (DSC = 1)

—

30.00

L1RQ valid before falling edge of L1TSYNC4

1.00

—

L1TCLK

L1GR setup time2

42.00

—

L1GR hold time

42.00

—

L1xCLK edge to L1SYNC valid (FSD = 00) CNT =

0000, BYT = 0, DSC = 0)

—0.00

The ratio SyncCLK/L1RCLK must be greater than 2.5/1.

These specs are valid for IDL mode only.

Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.

These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,

whichever is later.

Table 17. SI Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

L1RxD

(Input)

L1RCLK

(FE=0, CE=0)

(Input)

L1RCLK

(FE=1, CE=1)

(Input)

L1RSYNC

(Input)

L1ST

(Output)

RFSD=1

BIT0

71a

MPC850 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc

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