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MPC850 Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc |
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MPC850 Datasheet(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 72 page  MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 37 Bus Signal Timing Table 11 shows the reset timing for the MPC850. Table 11. Reset Timing Num Characteristic 50 MHz 66MHz 80 MHz FFACTOR Unit MinMax MinMax Min Max R69 CLKOUT to HRESET high impedance — 20.00 — 20.00 — 20.00 — ns R70 CLKOUT to SRESET high impedance — 20.00 — 20.00 — 20.00 — ns R71 RSTCONF pulse width 340.00 — 515.00 — 425.00 — 17.000 ns R72 —— ——— — — R73 Configuration data to HRESET rising edge set up time 350.00 — 505.00 — 425.00 — 15.000 ns R74 Configuration data to RSTCONF rising edge set up time 350.00 — 350.00 — 350.00 — — ns R75 Configuration data hold time after RSTCONF negation 0.00 — 0.00 — 0.00 — — ns R76 Configuration data hold time after HRESET negation 0.00 — 0.00 — 0.00 — — ns R77 HRESET and RSTCONF asserted to data out drive — 25.00 — 25.00 — 25.00 — ns R78 RSTCONF negated to data out high impedance. — 25.00 — 25.00 — 25.00 — ns R79 CLKOUT of last rising edge before chip tristates HRESET to data out high impedance. — 25.00 — 25.00 — 25.00 — ns R80 DSDI, DSCK set up 60.00 — 90.00 — 75.00 — 3.000 ns R81 DSDI, DSCK hold time 0.00 — 0.00 — 0.00 — — ns R82 SRESET negated to CLKOUT rising edge for DSDI and DSCK sample 160.00 — 242.00 — 200.00 — 8.000 ns |
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