RT3602AE datasheet(33/46 Pages) RICHTEK

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RT3602AE

DS3602AE-00 August 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Current Monitor, IMON

For each VR rail, the RT3602AE includes a current monitor

(IMON) function which can be used to detect over-current

protection and maximum processor current ICCMAX, and

also sets a part of current gain in the load-line setting. It

produces an analog voltage proportional to output current

between the IMON and VREF pins.

Load-Line (Droop) Setting

The G-NAVPTM topology can set load-line (droop) via the

current loop and voltage loop, the load-line is a slope

between load current ICC and output voltage Vsen as

shown in Figure 15. Figure 16 shows the voltage control

and current loop for MAIN and SA rails. By using both

loops, the load-line (droop) can be set easily. The load-

line set equation for MAIN and SA is :

OUT

DCR

(m )











where ROUT= RCS

ICC

VCOEE

Load line slope = -RLL

RLL x ICC

Figure 15. Load-Line (Droop)

Figure 16. Voltage Loop and Current Loop for MAIN and

SA Rails

Figure 17 shows the voltage control and current loop for

AUXI rail. By using both loops, the load-line (droop) can

be set easily. The load-line set equation for AUXI is :

IMON

DCR R





Where RCS = 2.15k

Figure 17. Voltage Loop and Current Loop for AUXI

The ki gain can be selected by SET [1:3] pins for individual

rail.

Compensator Design

The compensator of the RT3602AE doesn't need a

complex type II or type III compensator to optimize control

loop performance. It can adopt a simple type I

compensator (one pole, one zero) in the G-NAVPTM

topology to achieve constant output impedance design

for Intel IMVP8 ACLL specification. The one pole one zero

compensator is shown as Figure 18. The transfer function

of compensator should be design as following transfer

function to achieve constant output impedance, i.e. Zo(s)

= load-line slope in the entire frequency range :

CON

ESR

fsw

G(S)











where AI is current loop gain, RLL is load-line, fSW is

switching frequency and

ωESR is a pole that should be

located at 1/(COUT x ESR). Then, the C1 and C2 should

be designed as follows :

OUT

CESR

C1 =

C2 =







VID

DCR

ISENN

ISENP

ki/2

Voltage Loop

TON Generator

IMONA

ROUT

VREF

VSEN

RIMON

Current Loop

RCS

RX1

RX2

VID

DCR

IL1.2

ISEN[1:2]N

ISEN[1:2]P

ISEN1N + ISEN2N

ki/2

Voltage Loop

TON Generator

RIMON

IMON

RNTC

VREF

VSEN

Current Loop

RCS

RX1

RX2

RT3602AE Datasheet(PDF) 33 Page - Richtek Technology Corporation

RT3602AE Datasheet(HTML) 33 Page - Richtek Technology Corporation

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