CS42L52 datasheet(47/82 Pages) CIRRUS

47 / 82 page

DS680A1

CS42L52

6.6.5

DAC Interface Format

Configures the digital interface format for data on SDIN.

Note:

Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on

page 47).

6.6.6

Audio Word Length

Configures the audio sample word length used for the data into SDIN and out of SDOUT.

Note:

When the internal MCLK/LRCK ratio is set to 125 in master mode, the 32-bit data width option

for DSP Mode is not valid unless SCLK=MCLK.

6.7

Interface Control 2 (Address 07h)

6.7.1

SCLK equals MCLK

Configures the SCLK signal source for master mode.

Note:

This bit is only valid for MCLK = 12.0000 MHz.

6.7.2

SDOUT to SDIN Digital Loopback

Configures an internal loops the signal on the SDOUT pin to SDIN.

DACDIF[1:0]

DAC Interface Format

Left Justified, up to 24-bit data

I²S, up to 24-bit data

Right Justified

Reserved

Application:

“Digital Interface Formats” on page 36

AWL[1:0]

Audio Word Length

DSP Mode

Right Justified (DAC ONLY)

32-bit data

24-bit data

20-bit data

18-bit data

16-bit data

Application:

“DSP Mode” on page 36

543

Reserved

SCLK=MCLK

DIGLOOP

3ST_SP

INV_SWCH

BIASLVL2

BIASLVL1

BIASLVL0

SCLK=MCLK

Output SCLK

Re-timed signal, synchronously derived from MCLK

Non-retimed, MCLK signal

DIGLOOP

Internal Loopback

Disabled; SDOUT internally disconnected from SDIN

Enabled; SDOUT internally connected to SDIN

CS42L52 Datasheet(PDF) 47 Page - Cirrus Logic

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