CS42L52 datasheet(37/82 Pages) CIRRUS

37 / 82 page

DS680A1

CS42L52

The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-

cessible once RESET is high and the desired register settings can be loaded per the interface descriptions

in the “Register Description” on page 42.

Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin power-

ing up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then

applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-

ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the

MCLK/LRCK frequency ratio and normal operation begins.

4.9

Recommended Power-Up Sequence

1. Hold RESET low until the power supplies are stable.

2. Bring RESET high.

3. The default state of the PDN bit is ‘1’b. Load the desired register settings while keeping the PDN bit set

to ‘1’b.

4. Start MCLK to the appropriate frequency, as discussed in Section 4.6.

5. Set the PDN bit to ‘0’b.

6. Apply LRCK, SCLK and SDIN for normal operation to begin.

7. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to

prevent power glitch related issues.

4.10 Recommended Power-Down Sequence

To minimize audible pops when turning off or placing the CODEC in standby,

1. Mute the DAC’s and ADC’s.

2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a

fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary

to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.

3. Bring RESET low.

CS42L52 Datasheet(PDF) 37 Page - Cirrus Logic