TMPR4925 datasheet(176/590 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-6

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Single Address transfer from memory to an external I/O device (DMCCRn.MEMIO = “0”)

External memory Write operation to an address specified by the DMA Source Address

this time, the external I/O device drives the DATA signal instead of the TX4925.

Special attention must be paid to the timing design when the bus clock frequency is high or

when performing Burst transfer. Single Address transfer using Burst transfer with SDRAM is not

recommended.

8.3.3.4

DMADONE* Signal

The DMADONE* signal operates as either the DMA stop request input signal or the DMA

done signalling output signal, or may operate as both of these signals depending on the setting of

the DONE Control Field (DNCTRL) of the DMA Channel Control Register (DMCCRn).

The DMADONE* signal is shared by four channels. The DMADONE* channel is valid for a

channel when the DMAACK[n] signal for that channel is asserted.

If the DMADONE* channel is set to be used as an output signal (DMCCRn.DNCTRL = 10/11),

it will operate as follows depending on the setting of the Chain End bit (CHDN) of the DMA

Channel Control Register (DMCCRn).

When the Chain End bit (CHDN) is set, the DMADONE* signal is only asserted when the

DMAACK[n] signal for the last DMA transfer in the Link List Command Chain is asserted.

When the Chain End bit (CHDN) is cleared, the DMADONE* signal is asserted when the

DMAACK[n] signal for the last data transfer in a DMA transfer specified by the current DMA

Channel Register is asserted. Namely, if the Link List Command chain is used, there is one

assertion at the end of each data transfer specified by each Descriptor.

If the DMADONE* signal is set to be used as an input signal (DMCCRn.DNCTRL = 01/11),

DMA transfer can be set to end normally when the external device asserts the DMADONE* signal

when the DMAACK[n] signal of channel n is asserted. DMADONE* is asserted during

DMAACK[n] is not asserted, then unexpected operation occurs. When DMA transfer is

terminated by the DMADONE* assertion of the external device, the External DONE Assert bit

(DMCSRn.EXTDN) of the DMA Channel Status Register is set regardless of the setting of the

Chain End bit (CHDN) of the DMA Channel Control Register (DMCCRn). Operation is as

follows depending on the setting of the Chain End bit (CHDN).

When the Chain End bit (CHDN) is set, all DMA transfer for that chain is terminated. At this

time, the Normal Chain End bit (NCHNC) and the Normal Transfer End bit (NTRNFC) of the

DMA Channel Status Register are both set and the Transfer Active bit (DMCCRn.XFACT) of the

DMA Channel Control Register is cleared.

When the Chain End bit (CHDN) is cleared, only DMA transfer specified by the current DMA

Channel Register ends normally, and only the Normal Transfer End bit (NTRNFC) is set. When

the Chain Enable bit (CHNEN) of the DMA Channel Control Register (DMCCRn) is set, chain

transfer is executed and DMA transfer continues. When the Chain Enable bit (CHNEN) is cleared,

the Transfer Active bit (DMCCRn.XFACT) is cleared and the Normal Chain End bit (NCHNC) is

set.

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