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TMPR4925 Datasheet(PDF) 180 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 180 Page - Toshiba Semiconductor |
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180 / 590 page  Chapter 8 DMA Controller 8-10 (a) DMCCRn.USEXFSZ = “0” (b) DMCCRn.USEXFSZ = “1” Figure 8.3.2 Non-aligned Single Address Burst Transfer 8.3.8 Dual Address Transfer This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This applies to the following DMA transfer modes. • External I/O (Dual Address) transfer • Internal I/O DMA transfer • Memory-Memory Copy transfer 8.3.8.1 Channel Register Settings During Dual Address Transfer Table 8.3.3 shows restrictions of the Channel Register settings during Dual Address transfer. If these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit (CFERR) of the DMA Channel Status Register (DMCSRn) is set, and DMA transfer is not performed. If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the transfer setting size is 4 bytes or larger, then a value will be set in the DMA Source Address Register (DMSARn) that reflects the lower 2 bits. Similarly, if the setting of the DMA Destination Address Increment Register (DMDAIRn) is negative and the transfer setting size is 4 bytes or larger, then a value will be set in the DMA Destination Address Register (DMDARn) that reflects the lower 2 bits. 50 54 58 5c 64 68 6c 60 74 78 7c 70 00 04 08 0c 14 18 1c 10 24 28 2c 20 30 3 Words 4 Words 4 Words 4 Words 4 Words 4 Words DMCCRn.XFSZ = 0x4 32 Word Boundary 32 0 50 54 58 5c 64 68 6c 60 74 78 7c 70 00 04 08 0c 14 18 1c 10 24 28 2c 20 30 4 Words 4 Words (3 + 1) Words 4 Words 4 Words DMCCRn. XFSZ = 0x4 32 0 4 Words |
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