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TMPR4925 Datasheet(PDF) 184 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 184 Page - Toshiba Semiconductor |
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184 / 590 page ![]() Chapter 8 DMA Controller 8-14 (a) Address offset is equivalent (b) Address offset differs Figure 8.3.4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0) 50 54 58 5c 64 68 6c 60 74 78 7c 70 00 04 08 0c 14 18 1c 10 32 0 10 14 18 1c 24 28 2c 20 34 38 3c 30 40 44 48 4c 54 58 5c 50 32 0 Source Address FIFO (8 Double Words) Destination Address 50 54 58 5c 64 68 6c 60 74 78 7c 70 00 04 08 1c 14 18 1c 10 32 0 10 14 18 1c 24 28 2c 20 34 38 3c 30 40 44 48 4c 54 58 5c 50 32 0 24 28 2c 20 30 68 6c 70 64 60 |
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