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UPD6P9 Datasheet(PDF) 19 Page - Renesas Technology Corp

Part # UPD6P9
Description  MOS INTEGRATED CIRCUIT
PDF  73 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD6P9 Datasheet(HTML) 19 Page - Renesas Technology Corp

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17
µPD67, 67A, 68, 68A, 69
Data Sheet U14935EJ2V1DS
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
After reset, the register becomes 0000
×000BNote.
Note
×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID)
Remark VID: RAM retention detection voltage
Table 3-4. Control Register 0 (P3)
(1)
µPD67, 67A, 68, 68A
Bit
b7Note
b6Note
b5
b4
b3
b2
b1
b0
Name
DP (Data Pointer)
—
ID0
DP11
DP10
DP9
DP8
Setting
0
0
0
0
0
Not retainable Fixed to 0
11
111
Retainable
After reset
0
0
0
0
×
00
0
(2)
µPD69
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Name
DP (Data Pointer)
—
ID1
ID0
DP11
DP10
DP9
DP8
Setting
0
0
0
0
0
Not retainable Fixed to 0
Specification of
11
111
Retainable
PAGE0 to PAGE3
After reset
0
0
0
0
×
00
0
b0, b1:
Specify RAM pages 0 to 3 (
µPD69 only). Fixed to 0 in the µPD67, 67A, 68, and 68A.
ID1
ID0
RAM
00
Page 0
01
Page 1
10
Page 2
11
Page 3
b3:
RAM retention flag. For function details, refer to 3.3.1 RAM retention flag (bit 3 of P3).
b4 to b7: Specify the higher bits of the ROM data pointer (DP8 to DP11).
Note Set b7 and b6 to 0 in the case of the
µPD67 and 67A, and set b7 to 0 in the case of the µPD68 and 68A.
RAM
retention
flag
RAM
retention
flag



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