DSP56004SLASHD datasheet(29/82 Pages) FREESCALE

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Specifications

Internal Clocks

MOTOROLA

DSP56004/D, Rev. 3

2-5

INTERNAL CLOCKS

For each occurrence of TH, TL, TC or Icyc, substitute with the numbers in Table 2-4.

EXTERNAL CLOCK (EXTAL PIN)

The DSP56004 system clock is externally supplied via the EXTAL pin. Timings shown

in this document are valid for clock rise and fall times of 3 ns maximum.

Table 2-4

Internal Clocks

Characteristics

Symbol

Expression

Minimum

Maximum

Internal Operation Frequency

Internal Clock High Period

• with PLL disabled

• with PLL enabled and MF

≤ 4

• with PLL enabled and MF > 4

ETH

0.48

× T

0.467

× T

0.52

× T

0.533

× T

Internal Clock Low Period

• with PLL disabled

• with PLL enabled and MF

≤ 4

• with PLL enabled and MF > 4

ETL

0.48

× T

0.467

× T

0.52

× T

0.533

× T

Internal Clock Cycle Time

(DF /MF)

× ETC

Instruction Cycle Time

ICYC

× T

Table 2-5

External Clock (EXTAL Pin)

No.

Characteristics

Sym.

50 MHz

66 MHz

81 MHz

Unit

Min

Max

Min

Max

Min

Max

Frequency of External Clock (EXTAL Pin)

MHz

External Clock Input High—EXTAL Pin1

• with PLL disabled

(46.7%–53.3% duty cycle)

• with PLL enabled

(42.5%–57.5% duty cycle)

ETH

9.3

8.5

∞

235500

7.1

6.4

∞

235500

5.8

5.2

∞

235500

External Clock Input Low—EXTAL Pin1

• with PLL disabled

(46.7%–53.3% duty cycle)

• with PLL enabled

(42.5%–57.5% duty cycle)

ETL

9.3

8.5

∞

235500

7.1

6.4

∞

235500

5.8

5.2

∞

235500

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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