DSP56004SLASHD datasheet(16/82 Pages) FREESCALE

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DSP56004/D, Rev. 3

MOTOROLA

Signal/Connection Descriptions

Serial Host Interface (SHI)

SERIAL HOST INTERFACE (SHI)

The Serial Host Interface (SHI) has five I/O signals, which may be configured to

operate in either SPI or I2C mode. Table 1-8 lists the SHI signals.

Table 1-8

Serial Host Interface (SHI) signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

SCK

SCL

Input or

Output

Input or

Output

Tri-stated

SPI Serial Clock (SCK)

—The SCK signal is an output

when the SPI is configured as a master, and a Schmitt-

trigger input when the SPI is configured as a slave. When

the SPI is configured as a master, the SCK signal is

derived from the internal SHI clock generator. When the

SPI is configured as a slave, the SCK signal is an input,

and the clock signal from the external master

synchronizes the data transfer. The SCK signal is ignored

by the SPI if it is defined as a slave and the Slave Select

(SS) signal is not asserted. In both the master and slave

SPI devices, data is shifted on one edge of the SCK signal

and is sampled on the opposite edge where data is stable.

Edge polarity is determined by the SPI transfer protocol.

I2C Serial Clock (SCL)

—SCL carries the clock for bus

transactions in the I2C mode. SCL is a Schmitt-trigger

input when configured as a slave, and an open-drain

output when configured as a master. SCL should be

connected to VCC through a pull-up resistor. The

maximum allowed internally generated bit clock

frequency is

osc/

4 for the SPI mode and

osc/

6 for the

I2C mode where Fosc is the clock on EXTAL. The

maximum allowed externally generated bit clock

frequency is

osc/

3 for the SPI mode and

osc/

5 for the

I2C mode. This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for external

pull-up in this state).

Freescale Semiconductor, Inc.

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DSP56004/D Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc

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