DSP56004SLASHD datasheet(55/82 Pages) FREESCALE

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Specifications

Serial Host Interface (SHI) I2C Protocol Timing

MOTOROLA

DSP56004/D, Rev. 3

2-31

The Programmed Serial Clock Cycle, tI2CCP, is specified by the value of the HDM5–

HDM0 and HRS bits of the HCKR (SHI Clock control Register).

The expression for tI2CCP is:

where

•

HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-by-

eight prescaler is operational. When HRS is set, the prescaler is bypassed.

•

HDM5–HDM0 are the Divider Modulus Select bits.

•

A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.

In I2C mode, you may select a value for the Programmed Serial Clock Cycle from

× T

(HDM5–HDM0 = 2, HRS = 1)

1024

× T

(HDM5–HDM0 = $3F, HRS = 0).

The DSP56004 provides an improved I2C bus protocol. In addition to supporting the

100 kHz I2C bus protocol, the SHI in I2C mode supports data transfers at up to 1000

kHz. The actual maximum frequency is limited by the bus capacitances (CL),the pull-

up resistors (RP), (which affect the rise and fall time of SDA and SCL, (see table

below)), and by the input filters.

Consideration for programming the SHI Clock Control Register (HCKR) – Clock

Divide Ratio: the master must generate a bus free time greater than T172 slave when

operating with a DSP56004 SHI I2C slave.

The table below describes a few examples:

Table 2-14

Considerations for Programming the SHI Clock control Register (HCKR)

Conditions to be Considered

Resulting Limitations

Bus Load

Master

Oper-

ating

Freq.

Slave

Oper-

ating

Freq.

Master

Filter

Mode

Slave

Filter

Mode

T172

Slave

Min.

Perm-

issible

tI2CCP

T172

Master

Maximum

I2C Serial

Frequency

CL = 50 pF,

RP = 2 kΩ

81 MHz 81 MHz

Bypassed

Narrow

Wide

Bypassed

Narrow

Wide

36 ns

60 ns

95 ns

× T

41 ns

66 ns

103 ns

1010 kHz

825 kHz

634 kHz

CCP

HDM[5:0]

()

HRS

–

()

[]

Freescale Semiconductor, Inc.

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