DSP56004SLASHD datasheet(30/82 Pages) FREESCALE

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2-6

DSP56004/D, Rev. 3

MOTOROLA

Specifications

Phase Lock Loop (PLL) Characteristics

PHASE LOCK LOOP (PLL) CHARACTERISTICS

External Clock Cycle Time1

• with PLL disabled

• with PLL enabled

ETC

∞

409600

15.15

∞

409600

12.3

∞

409600

Instruction Cycle Time = Icyc = 2 × TC

• with PLL disabled

• with PLL enabled

ICYC

∞

819200

30.3

∞

819200

24.7

∞

819200

Note:

External Clock Input High and External Clock Input Low are measured at 50% of the input transition.

Figure 2-1 External Clock Timing

Table 2-6

Phase Lock Loop (PLL) Characteristics

Characteristics

Expression

Min

Max

Unit

VCO frequency when PLL enabled

× Ef

MHz

PLL external capacitor

(PCAP pin to VCCP)

× C

PCAP

@ MF

≤ 4

@ MF > 4

× 340

× 380

× 480

× 970

Note:

Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1.

The recommended value for Cpcap is 400 pF for MF

≤ 4 and 540 pF for MF > 4.

The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4.

Table 2-5

External Clock (EXTAL Pin) (Continued)

No.

Characteristics

Sym.

50 MHz

66 MHz

81 MHz

Unit

Min

Max

Min

Max

Min

Max

ETH

ETL

ETC

EXTAL

AA0250

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56004/D Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

DSP56004/D Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc

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