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DSP56004/D Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc |
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DSP56004/D Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 82 page  Specifications Serial Host Interface (SHI) SPI Protocol Timing MOTOROLA DSP56004/D, Rev. 3 2-23 SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING (CL = 50 pF; VIHS = 0.7 × VCC, VILS = 0.3 × VCC) Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing No. Characteristics Mode Filter Mode Expression 50 MHz 66 MHz 81 MHz Unit Min Max Min Max Min Max Tolerable Spike Width on Clock or Data In bypassed narrow wide — — — 0 20 100 — — — 0 20 100 — — — 0 20 100 ns ns ns 141 Minimum Serial Clock Cycle = tSPICC(min) For frequency below 33 MHz1 For frequency above 33 MHz1 CPHA = 0, CPHA = 12 CPHA = 1 master slave slave bypassed bypassed narrow wide bypassed narrow wide bypassed narrow wide 4 × T C 6 × T C 1000 2000 3 × T C 3 × T C+ 25 3 × T C + 85 3 × T C + 79 3 × T C + 431 3 × T C + 1022 — 120 1000 2000 60 85 145 139 491 1082 — — — — — — — — — — — 91 1000 2000 45 70 130 124 476 1067 — — — — — — — — — — — 74.1 1000 2000 37 62 122 116 468 1059 — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns 142 Serial Clock High Period CPHA = 0, CPHA = 12 CPHA = 1 master slave slave bypassed narrow wide bypassed narrow wide 0.5 × t SPICC –10 TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 50 28 51 63 70 246 541 — — — — — — — 35 23 46 58 63 239 534 — — — — — — — 27.0 20.3 43.3 55.3 58.5 235 530 — — — — — — — ns ns ns ns ns ns ns 143 Serial Clock Low Period CPHA = 0, CPHA = 12 CPHA = 1 master slave slave bypassed narrow wide bypassed narrow wide 0.5 × t SPICC –10 TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 50 28 51 63 70 246 541 — — — — — — — 35 23 46 58 63 239 534 — — — — — — — 27.0 20.3 43.3 55.3 58.5 235 550 — — — — — — — ns ns ns ns ns ns ns 144 Serial Clock Rise/Fall Time master slave 10 2000 — — 10 2000 — — 10 2000 — — 10 2000 ns ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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