TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

27

POST OFFICE BOX 1443

’C32 - 40

’C32 - 50

’C32 - 60

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

41

td(H3H-XF0H)

Delay time, H3 high to XF0 high

13

12

11

ns

† XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of

the store is driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store from

executing, the address of the store is not driven until the store can execute.

H3

H1

STRBx

R/W

A

D

RDY

XF0

Fetch

STFI or STII

Read

Execute

41

Decode

Figure 21. XF0 When Executing a STFI or STII