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TMS320C32PCMA50 Datasheet(PDF) 35 Page - Texas Instruments

Part # TMS320C32PCMA50
Description  DIGITAL SIGNAL PROCESSOR
PDF  45 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320C32PCMA50 Datasheet(HTML) 35 Page - Texas Instruments

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serial-port timing [P = tc(H)] (see Figure 29 and Figure 30)
NO
’C32 - 40
’C32 - 50
’C32 - 60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
65
td(H1-SCK)
Delay time, H1 high to internal CLKX / R high/low
13
10
8
ns
66
t (SCK)
Cycle time CLKX / R
CLKX / R ext
2.6P
2.6P
2.6P
ns
66
tc(SCK)
Cycle time, CLKX / R
CLKX / R int
2P
(232)P
2P
(232)P
2P
(232)P
ns
67
t (SCK)
Pulse duration CLKX / R high / low
CLKX / R ext
P + 10
P + 10
P + 10
ns
67
tw(SCK)
Pulse duration, CLKX / R high / low
CLKX / R int
[tc(SCK) /2]– 5
[tC(SCK) / 2] + 5
[tc(SCK) /2]– 5
[tc(SCK) /2]+5
[tc(SCK) /2]– 5
[tc(SCK) /2]+5
ns
68
tr(SCK)
Rise time, CLKX / R
7
6
5
ns
69
tf(SCK)
Fall time, CLKX / R
7
6
5
ns
70
td(DX)
Delay time CLKX to DX valid
CLKX ext
30
24
20
ns
70
td(DX)
Delay time, CLKX to DX valid
CLKX int
17
16
15
ns
71
t (DR)
Setup time DR before CLKR low
CLKR ext
9
9
8
ns
71
tsu(DR)
Setup time, DR before CLKR low
CLKR int
21
17
15
ns
72
th(DR)
Hold time DR from CLKR low
CLKR ext
9
7
6
ns
72
th(DR)
Hold time, DR from CLKR low
CLKR int
0
0
0
ns
73
td(FSX)
Delay time, CLKX to internal FSX
CLKX ext
27
22
20
ns
73
td(FSX)
y,
high / low
CLKX int
15
15
14
ns
74
t (FSR)
Setup time FSR before CLKR low
CLKR ext
9
7
6
ns
74
tsu(FSR)
Setup time, FSR before CLKR low
CLKR int
9
7
6
ns
75
th(FS)
Hold time, FSX / R input from CLKX / R
CLKX / R ext
9
7
6
ns
75
th(FS)
,
low
CLKX / R int
0
0
0
ns
76
t (FSX)
Setup time, external FSX before
CLKX ext
8 – P†
[tc(SCK) / 2]–10†
8–P†
[tc(SCK) / 2]–10†
8–P†
[tc(SCK) / 2]–10†
ns
76
tsu(FSX)
,
CLKX high
CLKX int
21 – P†
tc(SCK) /2†
21 – P†
tc(SCK) /2†
21 – P†
tc(SCK) /2†
ns
77
td(CH DX)V
Delay time, CLKX to first DX bit, FSX
CLKX ext
30†
24†
20†
ns
77
td(CH-DX)V
y,
,
precedes CLKX high
CLKX int
18†
14†
12†
ns
78
td(FSX-DX)V
Delay time, FSX to first DX bit, CLKX precedes FSX
30†
24†
20†
ns
79
td(DXZ)
Delay time, CLKX high to DX in the high-impedance
state following last data bit
17†
14†
12†
ns
† Assured from characterization but not tested



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