TMS320C32PCMA50 datasheet(10/45 Pages) TI

10 / 45 page

TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external memory interface (continued)

D For 32-bit-wide physical memory, all STRB0 and STRB1 pins function as byte-enable (chip-select) pins.

See Figure 4.

STRB0_B2/A –2

A14

A13

Data

A14

A13

STRB0_B3/A –1

Data

A13

A14

32-Bit Data Bus

Data

A13

A14

STRB0_B0

STRB0_B1

A13

A14

Data

Figure 4. ’C32 With 32-Bit-Wide External Memory

For more detailed information and examples see

TMS320C32 Addendum to the TMS320C3x User’s Guide

(literature number SPRU132) and

Interfacing Memory to the TMS320C32 DSP Application Report (literature

number SPRA040).

D The IOSTRB control signal, like STRB0 and STRB1, also is mapped to a specific range of addresses but

it is a single signal that can access only 32-bit data from 32-bit-wide memory. Its range of addresses appears

in the TMS320C32 memory map, shown in Figure 8. The IOSTRB bus timing is different from the STRB0

and STRB1 bus timings to accommodate slower I/O peripherals.

TMS320C32PCMA50 Datasheet(PDF) 10 Page - Texas Instruments