TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

37

POST OFFICE BOX 1443

NO

’C32 - 40

’C32 - 50

’C32 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

80

tsu(HOLD)

Setup time, HOLD before H1 low

13

10

8

ns

81

tv(HOLDA)

Valid time, HOLDA after H1 low

0†

9

0†

7

0†

6

ns

82

tw(HOLD)

Pulse duration, HOLD low

2P

2P

2P

ns

83

tw(HOLDA)

Pulse duration, HOLDA low

P–5†

P–5†

P–5†

ns

84

td(H1L-SH)H

Delay time, H1 low to STRBx high for a HOLD

0‡

9

0‡

7

0‡

6

ns

84.1

td(H1H-IOS)H Delay time, H1 high to IOSTRB high for a HOLD

0‡

9

0‡

7

0‡

6

ns

85

tdis(H1L-S)

Disable time, H1 low to STRBx or IOSTRB (in the

high-impedance state)

0‡

9†

0‡

8†

0‡

7†

ns

86

ten(H1L-S)

Enable time, H1 low to STRBx or IOSTRB active

0‡

9

0‡

7

0‡

6

ns

87

tdis(H1L-RW)

Disable time, H1 low to R/W in the

high-impedance state

0†

9†

0†

8†

0†

7†

ns

88

ten(H1L-RW)

Enable time, H1 low to R/W (active)

0†

9

0†

7

0†

6

ns

89

tdis(H1L-A)

Disable time, H1 low to A in the high-impedance

state

0‡

10†

0‡

8†

0‡

7†

ns

90

ten(H1L-A)

Enable time, H1 low to A valid

0‡

13

0‡

12

0‡

11

ns

91

tdis(H1H-D)

Disable time, H1 high to D disabled in the

high-impedance state

0‡

9†

0‡

8†

0‡

7†

ns

† Assured from characterization but not tested

‡ Not tested

NOTE 6: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact

sequence shown occurs; otherwise, an additional delay of one clock cycle can occur. The NOHOLD bit of the primary-bit-control register

overwrites the HOLD signal.