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TMS320C32PCMA50 Datasheet(PDF) 41 Page - Texas Instruments |
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TMS320C32PCMA50 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 45 page ![]() TMS320C32 DIGITAL SIGNAL PROCESSOR SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996 41 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing for timer pin [P = tc(H)] (see Figure 35)† NO ’C32 - 40 UNIT NO. MIN MAX UNIT 99 tsu(TCLKH1L) Setup time, TCLK external before H1 low 10 ns 100 th(TCLKH1L) Hold time, TCLK external after H1 low 0 ns 101 td(TCLKH1H) Delay time, H1 high to TCLK internal valid 9 ns 102 t (TCLK) Cycle time TCLK TCLK external 2.6P ns 102 tc(TCLK) Cycle time, TCLK TCLK internal 2P (232)P‡ ns 103 t (TCLK) Pulse duration TCLK high / low TCLK external P + 10 ns 103 tw(TCLK) Pulse duration, TCLK high / low TCLK internal [tc(TCLK) /2]–5 [tc(TCLK) / 2]+5 ns † Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous input clock. ‡ Assured by design but not tested NO ’C32 - 50 UNIT NO. MIN MAX UNIT 99 tsu(TCLKH1L) Setup time, TCLK external before H1 low 8 ns 100 th(TCLKH1L) Hold time, TCLK external after H1 low 0 ns 101 td(TCLKH1H) Delay time, H1 high to TCLK internal valid 9 ns 102 t (TCLK) Cycle time TCLK cycle time TCLK external 2.6P ns 102 tc(TCLK) Cycle time, TCLK cycle time TCLK internal 2P (232)P‡ ns 103 t (TCLK) Pulse duration TCLK high / low TCLK external P + 10 ns 103 tw(TCLK) Pulse duration, TCLK high / low TCLK internal [tc(TCLK) /2]–5 [tc(TCLK) / 2]+5 ns † Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous input clock. ‡ Assured by design but not tested NO ’C32 - 60 UNIT NO. MIN MAX UNIT 99 tsu(TCLKH1L) Setup time, TCLK external before H1 low 6 ns 100 th(TCLKH1L) Hold time, TCLK external after H1 low 0 ns 101 td(TCLKH1H) Delay time, H1 high to TCLK internal valid 8 ns 102 t (TCLK) Cycle time TCLK cycle time TCLK external 2.6P ns 102 tc(TCLK) Cycle time, TCLK cycle time TCLK internal 2P (232)P‡ ns 103 t (TCLK) Pulse duration TCLK high / low TCLK external P + 10 ns 103 tw(TCLK) Pulse duration, TCLK high / low TCLK internal [tc(TCLK) /2]–5 [tc(TCLK) / 2]+5 ns † Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous input clock. ‡ Assured by design but not tested 101 101 100 TCLKx H1 H3 99 102 103 Figure 35. Timing for Timer Pin |
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