PCD5003 datasheet(19/44 Pages) PHILIPS

19 / 44 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG Paging Decoder

PCD5003

7.28

Real time clock

The PCD5003 provides a periodic reference pulse at

output REF. The frequency of this signal can be selected

by SPF programming:

• 32768 Hz

• 50 Hz (square-wave)

• 2Hz

• 1⁄60 Hz.

The 32768 Hz signal does not have a fixed period: it

consists of 32 pulses distributed over 75 main oscillator

cycles at 76.8 kHz. The timing is shown in Fig.14.

When programmed for 1

⁄60 Hz (1 pulse per minute) the

pulse at output REF is held off while the receiver is

enabled.

Except for the 50 Hz frequency the pulse width tRFP is

equal to one decoder clock period.

The real time clock counter runs continuously irrespective

of the operating condition of the PCD5003. It contains a

seconds register (maximum 59) and a 1

⁄100 second

the I2C-bus. The bit allocation of both registers is shown in

Tables 16 and 17.

Table 16 Real time clock; seconds register (01H;

read/write)

BIT

(MSB D7)

VALUE

DESCRIPTION

−

16 s

−

32 s

not used: ignored when written,

undetermined when read

not used: ignored when written,

undetermined when read

Table 17 Real time clock; 1

⁄100 second register (02H;

read/write)

7.29

Periodic interrupt

A periodic interrupt can be realised with the Periodic

Interrupt Counter. This 8-bit counter is incremented every

⁄100 second and produces an interrupt when it reaches the

value stored in the Periodic Interrupt Modulus register.

The Counter register is then reset and counting continues.

Operation is started by writing a non-zero value to the

Modulus register. Writing a zero will stop interrupt

generation immediately and will halt the Periodic Interrupt

Counter after 2.55 seconds.

The Modulus register is write-only, the Counter register

can only be read. Both registers have the same index

address (05H).

7.30

Received call delay

Call reception causes both the Periodic Interrupt Modulus

and the Counter register to be reset.

Since the Periodic Interrupt Counter runs for another

2.55 seconds after a reset, the received call delay

(in 1

⁄100 second units) can be determined by reading the

Counter register.

BIT

(MSB D7)

VALUE

DESCRIPTION

−

0 01 s

−

0.02 s

−

0.04 s

−

0.08 s

−

0.16 s

−

0.32 s

−

0.64 s

not used: ignored when written,

undetermined when read

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