PCD5003 datasheet(27/44 Pages) PHILIPS

27 / 44 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG Paging Decoder

PCD5003

7.55

Synthesizer programming data

Data for programming a PLL synthesizer via pins ZSD,

ZSC and ZLE can be stored in row 1 of the EEPROM.

Six bytes are available starting from address 08H.

Data is transferred in two serial blocks of 24 bits each,

starting with bit 0 (MSB) of block 1. Any unused bits must

be programmed at the beginning of a block.

7.56

Identiﬁer storage allocation

Up to 6 different identifiers can be stored in EEPROM for

matching with incoming data. The PCD5003 can

distinguish two types of identifiers:

• User addresses (RIC)

• User Programmable Sync Words (UPSW).

Identifiers are stored in EEPROM rows 2, 3 and 4. Each

identifier location consists of 3 bytes in the same column.

The identifier number is equal to the column number + 1.

Only the last 4 identifiers (numbers 3 to 6) can be

programmed as a UPSW. Identifiers 1 and 2 always

represent RICs. A UPSW represents an unused address

and must differ by more than 6 bits from preamble to

guarantee detection.

The standard POCSAG sync word is always enabled and

has identifier number 7.

Table 26 shows the memory locations of the 6 identifiers.

The bit allocation per identifier is given in Table 27.

Table 25 Synthesizer programming data (EEPROM address 08H to 0DH)

Table 26 Identiﬁer storage allocation (EEPROM address 10H to 25 H)

ADDRESS (HEX)

BIT (MSB: D7)

DESCRIPTION

D7 to D0

bits 0 to 7 of data block 1 (bit 0 is MSB)

D7 to D0

bits 8 to 15

D7 to D0

bits 16 to 23

D7 to D0

bits 0 to 7 of data block 2 (bit 0 is MSB)

D7 to D0

bits 8 to 15

D7 to D0

bits 16 to 23

ADDRESS (HEX)

BYTE

DESCRIPTION

10 to 15

identiﬁer number 1 to 6

18 to 1D

identiﬁer number 1 to 6

20 to 25

identiﬁer number 1 to 6

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