PCD5003 datasheet(29/44 Pages) PHILIPS

29 / 44 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG Paging Decoder

PCD5003

OPERATING INSTRUCTIONS

8.1

Reset conditions

When the PCD5003 is reset by applying a HIGH-level on

input RST, the condition of the decoder is as follows:

• OFF status (irrespective of DON input level)

• REF output frequency 32768 Hz

• All internal counters reset

• Status/control register reset

• INT output at LOW-level

• No alert transducers selected

• LED, VIB and ATH outputs at LOW level

• ATL output high impedance

• SDA, SCL inputs high impedance

• Voltage converter disabled.

Within tRSU after release of the reset condition (RST LOW)

the programmed functions are activated. The settings

affecting the external operation of the PCD5003 are as

follows:

• REF output frequency

• Voltage converter

• INT output polarity

• Signal test mode.

When input DON is HIGH, the decoder starts operating in

ON status immediately following tRSU.

8.2

Power-on reset circuit

During power-up of the PCD5003 a HIGH level of

minimum duration tRST =50 µs must be applied to pin

RST. This is to prevent EEPROM corruption which might

otherwise occur because of the undefined contents of the

Control register.

The reset signal can be applied by the external

microcontroller or by an RC power-on reset circuit on pin

RST (C to VPR, R to VSS). Such an RC-circuit should have

a time constant of at least 3tRST = 150 µs.

Input RST has an internal high-ohmic pull-down resistor

(nominal 2 M

Ω at 2.5 V supply) which could be used

together with a suitable external capacitor connected to

VPR to create a power-on reset signal. However, since this

pull-down resistor varies considerably with processing and

supply voltage, the resulting time constant is inaccurate.

A more accurate reset duration can be realised with an

additional external resistor connected to VSS.

Recommended minimum values in this case are

C = 2.2 nF and R = 100 k

Ω (see Fig.15).

8.3

Reset timing

The start-up time for the crystal oscillator may exceed

1 second (typ. 800 ms). It is advised to apply a reset

condition at least during the first part of this period.

The minimum reset pulse duration tRST is 50 µs.

During reset the oscillator is active, but clock signals are

inhibited internally. Once the reset condition is released

the end of the oscillator start-up period can be detected by

a rising edge on output INT.

During a reset the voltage converter clock (Vclk) is held at

zero. The resulting output voltage drop may cause

problems when the external resetting device is powered by

the internal voltage doubler. A sufficiently large buffer

capacitor between output VPO and VSS must be provided

to supply the microcontroller during reset. The voltage at

VPO will not drop below VDD − 0.7 V.

Immediately after a reset all programmable internal

functions will start operating according to a programmed

value of 0. During the first 8 full clock cycles (tRSU) all

programmed values are loaded from EEPROM.

After reset the receiver outputs RXE and ROE become

active immediately, if DON is HIGH and the synthesizer is

disabled. When the synthesizer is enabled, RXE and ROE

will only become active after the second pulse on ZLE

completes the loading of synthesizer data.

The full reset timing is shown in Fig.11. The start-up timing

including synthesizer programming is given in Fig.12.

8.4

Initial programming

A newly-delivered PCD5002 has EEPROM contents which

are undefined. The EEPROM should therefore be

programmed, followed by a reset to activate the SPF

settings, before any attempt is made to use the device.

PCD5003 Datasheet(PDF) 29 Page - NXP Semiconductors

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