PCD5003 datasheet(36/44 Pages) PHILIPS

36 / 44 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG Paging Decoder

PCD5003

Notes

1. 32768 Hz reference signal: 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods

(pulse duration: tRFP). The timing is shown in Fig.14.

2. 50 Hz reference signal: square-wave.

3. The fall time may be faster than prescribed in the I2C-bus specification for very low load capacitance values.

To increase the fall time external capacitance is required.

4. Duration depends on programmed bit rate; after reset tZSU = 1.5 bits.

5. Nominal values; pause in 12th data bit (see Table 12).

POCSAG data timing (1200 bits/s)

fDI

data input rate

SPF byte 01H; bits D5, D4 = 1 0

−

1200

−

bits/s

tBIT

bit duration

−

833.3

−µs

tCW

codeword duration

−

26.7

−

tPA

preamble duration

480

−−

tBAT

batch duration

−

453.3

−

POCSAG data timing (2400 bits/s)

fDI

data input rate

SPF byte 01H; bits D5, D4 = 1 1

−

2400

−

bits/s

tBIT

bit duration

−

416.6

−µs

tCW

codeword duration

−

13.3

−

tPA

preamble duration

240

−−

tBAT

batch duration

−

226.6

−

Synthesizer control

tZSU

synthesizer set-up duration

oscillator running; note 4

−

bits

fZSC

output clock frequency

note 5

−

38400

−

tZCL

clock pulse duration

−

13.02

−µs

tZSD

data bit duration

note 5

−

26.04

−µs

tZDS

data bit set-up time

−

13.02

−µs

tZDL1

data load enable delay

−

91.15

−µs

tZLE

load enable pulse duration

−

13.02

−µs

tZDL2

inter block delay

−

117.19

−µs

SYMBOLS

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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