PCD5003 datasheet(24/44 Pages) PHILIPS

24 / 44 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG Paging Decoder

PCD5003

7.48

EEPROM access limitations

Since the EEPROM address pointer is used during data

decoding, the EEPROM may not be accessed while the

receiver is active (RXE = 1). It is advised to switch to OFF

state before accessing the EEPROM.

The EEPROM cannot be written unless the EEPROM

programming enable bit (bit D1) in the control register is

set.

For writing a minimum supply voltage VPG is required

(2.0 V typ.). The supply current needed during writing (IPG)

will be

≈500 µA.

Any modified SPF settings (bytes 0 to 3) only take effect

after a decoder reset. Modified identifiers are active

immediately.

7.49

EEPROM read operation

EEPROM read operations must start at a valid address in

the non-contiguous memory map. Single-byte or block

reads are permitted.

7.50

EEPROM write operation

EEPROM write operations must always take place in

blocks of 6 bytes, starting at the beginning of a row.

Programming a single byte will reset the other bytes in the

same row. Modifying a single byte in a row requires

re-writing the unchanged bytes with their old contents.

After writing each block a pause of maximum 7.5 ms is

required to complete the programming operation

internally. During this time the external microcontroller

may generate an I2C-bus stop condition. If another I2C-bus

transfer is started the decoder will pull SCL LOW during

this pause.

After writing the EEPROM programming enable bit (D1) in

the control register must be reset.

7.51

Invalid write address

When an invalid write address is used, the column counter

bits (D2 to D0) are forced to zero before being loaded into

the address pointer. The row counter bits are used

normally.

7.52

Incomplete programming sequence

A programming sequence may be aborted by an I2C-bus

stop condition. Next, the EEPROM programming enable

bit (D1) in the control register must be reset.

Any bytes received of the last 6-byte block will be ignored

and the contents of this (incomplete) EEPROM block will

remain unchanged.

7.53

Unused EEPROM locations

A total of 20 EEPROM bytes is available for general

purpose storage (see Table 19).

Fig.10 EEPROM organization and access.

handbook, full pagewidth

COLUMN

ROW

ADDRESS

POINTER

ROW COLUMN

I/O REGISTER

SPF bits

Synthesizer data

Identifiers

unused bytes

MLC254

PCD5003 Datasheet(PDF) 24 Page - NXP Semiconductors

PCD5003 Datasheet(HTML) 24 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL