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VT8235 Datasheet(PDF) 22 Page - VIA Technologies, Inc.

Part # VT8235
Description  V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE
PDF  145 Pages
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Manufacturer  VIA [VIA Technologies, Inc.]
Direct Link  https://www.viatech.com/en/
Logo VIA - VIA Technologies, Inc.

VT8235 Datasheet(HTML) 22 Page - VIA Technologies, Inc.

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VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002
-16-
Pin Descriptions
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Internal Keyboard Controller
Signal Name
Pin #
I/O
PU
Signal Description
MSCK
/ IRQ1
W2
IO / I
PU
MultiFunction Pin
(Internal mouse controller enabled by Rx51[1])
Rx51[2]=1 Mouse Clock. From internal mouse controller.
Rx51[2]=0 Interrupt Request 1. Interrupt input 1.
MSDT
/ IRQ12
W1
IO / I
PU
MultiFunction Pin
(Internal mouse controller enabled by Rx51[1])
Rx51[2]=1 Mouse Data. From internal mouse controller.
Rx51[2]=0 Interrupt Request 12. Interrupt input 12.
KBCK
/ KA20G
V3
IO / I
PU
MultiFunction Pin
(Internal keyboard controller enabled by
Rx51[0])
Rx51[0]=1 Keyboard Clock. From internal keyboard controller
Rx51[0]=0 Gate A20. Input from external keyboard controller.
KBDT
/ KBRC
V2
IO / I
PU
MultiFunction Pin
(Internal keyboard controller enabled by
Rx51[0])
Rx51[0]=1 Keyboard Data. From internal keyboard controller.
Rx51[0]=0 Keyboard Reset. From external keyboard controller
(KBC) for CPURST# generation
KBCS#
/ ROMCS# / strap
AF12
O / O
Keyboard Chip Select
(Rx51[0]=0).
To external keyboard
controller chip. Strap high to enable LPC ROM:
Note: KBCK, KBDT, MSCK, and MSDT are powered by the VSUS33 suspend voltage plane.
ISA Subset / Parallel BIOS ROM Interface
Signal Name
Pin #
I/O
PU
Signal Description
ROMCS#
/ KBCS# /
strap
AF12
O
ROM Chip Select
(Rx51[0]=1). Chip Select to the BIOS ROM.
Strap high to enable LPC ROM.
SPKR
/ strap
AE9
O
Speaker.
Strap low to enable (high to disable) CPU frequency
strapping.
MEMR#
AE12
O
Memory Read.
MEMW#
AF10
O
Memory Write.
IOR#
AC10
O
I/O Read.
IOW#
AD9
O
I/O Write.
IORDY
/ GPI19
AD10
I
I/O Ready.
Used to insert wait states in I/O or memory cycles.
RxE5[0] = 0
SOE#
/ strap
AD12
O
XD Bus Tranceiver Output Enable.
Strap low to enable auto
reboot.
XD[7-0]
AD13, AE13,
AF13, AD14,
AE14, AF14,
AC13, AC14
IO
XD Bus.
For input of BIOS ROM data or data from other on-board
I/O or memory devices.
SA[19-16]
/ GPO[19-16]
/ straps
AC11, AD11,
AE11, AF11
O
PD
System Address 19-16.
Strap states are passed to North Bridge via
VAD[3-0]. Functions as SA[19-16] if RxE4[5] = 0.
SA[15-0]
/ SDD[15-0]
(see pin list)
O
System Address 15-0.



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