VT8235 datasheet(69/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-63-

Device 17 Function 0 Bus Control Registers

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Offset 48 – Read Pass Write Control ...............................RW

APIC FSB Fixed at Low DW

Disable (Address Bit-2 not masked)...... default

Enable (force A2 from APIC FSB to low)

Address bit A2 controls whether data is in the lower

(0) or upper (1) doubleword of a quadword sent to

the CPU. When this bit is enabled, A2 is masked

which means it is always 0 to select the lower

doubleword.

6-4

Reserved

........................................ always reads 0

AC97 / LPC Read Pass Write

Disable (a read cannot be performed before a

preceeding write has been completed) .. default

Enable (internal AC97 and LPC devices are

allowed to perform a read before a preceeding

write)

IDE Read Pass Write

Disable (a read cannot be performed before a

preceeding write has been completed) .. default

Enable (the internal IDE controller is allowed

to perform a read before a preceeding write)

USB Read Pass Write

Disable (a read cannot be performed before a

preceeding write has been completed) .. default

Enable (the internal USB controllers are

allowed to perform a read before a preceeding

write)

NIC Read Pass Write

Disable (a read cannot be performed before a

preceeding write has been completed) .. default

Enable (the internal LAN controller is allowed

to perform a read before a preceeding write)

Offset 49 – CCA Control .................................................. RW

Reserved

........................................always reads 0

South Bridge Internal Master Devices Priority

Higher Than External PCI Master

Disable ................................................... default

Enable

The “CCA” is an internal arbiter that controls the

priority of external PCI masters vs. internal master

devices. Normally priority is the same for internal

and external PCI master devices, but when this bit is

enabled, internal master devices are given higher

priority than external PCI masters (3/4 : 1/4).

CCA Clean to Mask Off IRQ

Controls whether interrupt requests are gated until

data is written to memory.

Disable ................................................... default

Enable

4-3

Reserved (Do Not Program)

....................default = 0

WSC Mask Off INTR

Controls whether INTR is masked until write snoop

is complete.

Disable ................................................... default

Enable

1-0

Reserved (Do Not Program)

....................default = 0

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