VT8235 datasheet(68/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-62-

Device 17 Function 0 Bus Control Registers

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ISA Bus Control

Offset 40 - ISA Bus Control (00h) ....................................RW

ISA Command Delay

Normal .................................................. default

Extra

I/O Recovery Time

The number of clocks between 2 I/O commands

Disable .................................................. default

Enable (Rx4C[7:6] determines the # of clocks)

ROM Wait States

1 Wait State ........................................... default

0 Wait States

ROM Write

Disable (ROM writes are ignored) ........ default

Enable (ROM can be written)

Double DMA Clock

DMA clock runs at 4 MHz .................... default

DMA clock runs at 8 MHz

4D0 / 4D1 Port Configuration

Controls whether ports 4D0 / 4D1 can be configured.

Ports 4D0 / 4D1 determine whether IRQ requests are

edge or level triggerred (4D0[7-0] for IRQ7-0,

4D1[7-0] for IRQ15-8) (0 = level, 1 = edge).

Disable .................................................. default

Enable

DMA / Interrupt / Timer Shadow Register Read

Disable .................................................. default

Enable (shadow register values can be read)

Double ISA Bus Clock

Bus clock runs at PCLK / 4 (8 MHz) .... default

Bus clock runs at PCLK / 2 (16 MHz)

Offset 41 – BIOS ROM Decode Control (00h)................RW

Setting these bits to 1 enables the indicated address range to be

included in the ROMCS# decode:

000E0000h-000EFFFFh

.............. default=0 (disable)

FFF00000h-FFF7FFFFh

............ default=0 (disable)

FFE80000h-FFEFFFFFh

............ default=0 (disable)

FFE00000h-FFE7FFFFh

............ default=0 (disable)

FFD80000h-FFDFFFFFh

.......... default=0 (disable)

FFD00000h-FFD7FFFFh

........... default=0 (disable)

FFC80000h-FFCFFFFFh

.......... default=0 (disable)

FFC00000h-FFC7FFFFh

............ default=0 (disable)

Note:

ROMCS# is always active when ISA addresses

FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded.

Offset 42 – Line Buffer Control (00h) ............................. RW

ISA Master DMA Line Buffer

Controls whether the DMA line buffer is used.

Disable ................................................... default

Enable.

Master DMA waits until the line

buffer is full (8 DWords) before transmitting

data (bit-6 must also be enabled to insure that

there are no coherency issues).

Gate Interrupt Until Line Buffer Flush Complete

This bit should be enabled if bit-7 is enabled.

Disable ................................................... default

Enable. IRQs are gated until the line buffer is

flushed to insure that there are no coherency

issues.

Flush Line Buffer for Interrupt

This bit controls whether the line bufer is flushed

when an interrupt request is generated.

This bit

should be enabled if bit-7 is enabled.

Disable ................................................... default

Enable

Uninterruptable Burst Read

Disable ................................................... default

Enable. The PCI bus is not granted to DMA

until burst read transactions from the north

bridge are completed.

Gate IRQ Until Line Bufer Flush Completed

Disable ................................................... default

Enable

2-0

Reserved

........................................always reads 0

Offset 43 – Delay Transaction Control (00h).................. RW

7-4

Reserved (Do Not Program)

....................default = 0

Delayed Transactions (PCI Spec Rev 2.1)

This

bit

controls whether

delayed

transactions

(delayed read / write and posted write) are enabled.

Disable ................................................... default

Enable

Only Posted Write

This bit controls whether posted write is enabled, as

opposed to bit-3 which controls whether delayed read

/ write as well as posted write are enabled.

Disable ................................................... default

Enable

Write Delay Transaction Timeout Timer

When enabled, if a delayed transaction (write cycle

only) is not retried after 2

PCI clocks, the

transaction is terminated.

Disable ................................................... default

Enable

Read Delay Transaction Timeout Timer

When enabled, if a delayed transaction (read cycle

only) is not retried after 2

PCI clocks, the

transaction is terminated.

Disable ................................................... default

Enable

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