AMD-K6-2ESLASH233AMZ datasheet(34/332 Pages) AMD

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Internal Architecture

Chapter 2

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

Long Decoder. The commonly-used x86 instructions that are

greater than seven bytes but not more than 11 bytes long, and

the x86 instructions that are slightly less common and are up to

seven bytes long are handled by the long decoder. The long

decoder only performs one decode per clock and generates up

to four RISC86 operations.

Vector Decoder. All other translations (complex instructions,

serializing conditions, interrupts and exceptions, etc.) are

handled by a combination of the vector decoder and RISC86

operation sequences fetched from an on-chip ROM. For

complex operations, the vector decoder logic provides the first

set of RISC86 operations and a vector (initial ROM address) to a

sequence of further RISC86 operations. The same types of

RISC86 operations are fetched from the ROM as those that are

generated by the hardware decoders.

Note: Although all three sets of decoders are simultaneously fed a

copy of the instruction buffer contents, only one of the three

types of decoders is used during any one decode clock.

Grouped Operations. The decoders or the RISC86 sequencer

always generate a group of four RISC86 operations. For decodes

that cannot fill the entire group with four RISC86 operations,

RISC86 NOP operations are placed in the empty locations of

the grouping. For example, a long-decoded x86 instruction that

converts to only three RISC86 operations is padded with a

single RISC86 NOP operation and then passed to the scheduler.

Up to six groups, or 24 RISC86 operations, can be placed in the

scheduler at a time.

Floating Point Instructions. All of the common, and a few of the

uncommon, floating-point instructions (also known as ESC

instructions) are hardware decoded as short decodes. This

decode generates a RISC86 floating-point operation and,

optionally, an associated floating-point load or store operation.

Floating-point or ESC instruction decode is only allowed in the

first short decoder, but non-ESC instructions, excluding MMX

instructions, can be decoded simultaneously by the second

short decoder along with an ESC instruction decode in the first

short decoder.

MMX and 3DNow!™ Instructions. All of the MM X and 3DNow!

instructions, with the exception of the EMMS, FEMMS, and

PREFETCH instructions, are hardware decoded as short

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