AMD-K6-2ESLASH233AMZ datasheet(75/332 Pages) AMD

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Chapter 3

Software Environment

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

reg16/32—word or doubleword integer register defined by

instruction byte(s) or bits 5, 4, and 3 of the modR/M byte

Opcode Bytes

The second and third columns list all applicable opcode bytes.

ModR/M Byte

The fourth column lists the modR/M byte when used by the

instruction. The modR/M byte defines the instruction as a

as mm (memory form), mm can only be 10b, 01b or 00b.

Decode Type

The fifth column lists the type of instruction decode — short,

long, and vector. The AMD-K6-2E processor decode logic can

process two short, one long, or one vector decode per clock.

RISC86 Operation

The sixth column lists the type of RISC86 operation(s) required

for the instruction. The operation types and corresponding

execution units are as follows:

alu—either of the integer execution units

alux—integer X execution unit only

branch—branch condition unit

float—floating-point execution unit

limm—load immediate, instruction control unit

load, fload, mload—load unit

meu—Multimedia execution units for MMX and 3DNow!

instructions

store, fstore, mstore—store unit

Table 12. Integer Instructions

Instruction Mnemonic

First

Byte

Second

Byte

ModR/M

Byte

Decode

Type

RISC86

Operations

AAA

37h

vector

AAD

D5h

0Ah

vector

AAM

D4h

0Ah

vector

AAS

3Fh

vector

ADC mreg8, reg8

10h

11-xxx-xxx

vector

ADC mem8, reg8

10h

mm-xxx-xxx

vector

ADC mreg16/32, reg16/32

11h

11-xxx-xxx

vector

ADC mem16/32, reg16/32

11h

mm-xxx-xxx

vector

ADC reg8, mreg8

12h

11-xxx-xxx

vector

ADC reg8, mem8

12h

mm-xxx-xxx

vector

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