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AMD-K6-2E/233AMZ Datasheet(PDF) 104 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ Datasheet(HTML) 104 Page - Advanced Micro Devices |
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104 / 332 page ![]() 86 Signal Descriptions Chapter 5 AMD-K6™-2E Processor Data Sheet 22529B/0—January 2000 Preliminary Information 5.2 A20M# (Address Bit 20 Mask) Pin Attribute Input Pin Location AK-08 Summary A20M# is used to simulate the behavior of the 8086 when running in real mode. The assertion of A20M # causes the processor to force bit 20 of the physical address to 0 prior to accessing the cache or driving out a memory bus cycle. The clearing of address bit 20 maps addresses that wrap above 1 Mbyte to addresses below 1 Mbyte. Sampled The processor samples A20M # as a level-sensitive input on every clock edge. The system logic can drive the signal either sync hr o n ousl y or async h r o nousl y. I f i t is ass e r t ed asynchronously, it must be asserted for a minimum pulse width of two clocks. The following list explains the effects of the processor sampling A20M# asserted under various conditions: s Inquire cycles and writeback cycles are not affected by the state of A20M#. s The assertion of A20M# in system management mode (SMM) is ignored. s When A20M# is sampled asserted in protected mode, it causes unpredictable processor operation. A20M# is only defined in real mode. s To ensure that A20M# is recognized before the first ADS# occurs following the negation of RESET, A20M# must be sampled asserted on the same clock edge that RESET is sampled negated or on one of the two subsequent clock edges. s To ensure A20M# is recognized before the execution of an instruction, a serializing instruction must be executed between the instruction that asserts A20M# and the targeted instruction. |
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