33989 datasheet(36/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 19. HS1 Operation when Cyclic Sense is Selected

Low Power Mode Control Register (LPC)

This register controls:

• The state of HS1 in Stop and Sleep mode (HS1

permanently off or HS1 cyclic)

• Enable or disable the forced wake-up function (SBC

automatic wake-up after time spend in Sleep or Stop

modes, time is defined by the TIM2 register)

• Enable or disable the sense of the wake-up inputs (Lx) at

sampling point of the Cyclic Sense period (LX2HS1 bit).

Please refer to the Cyclic Sense Wake-up discussion for

details of the LPC register setup required for proper Cyclic

Sense or direct wake-up operation.

Table 27. TIM1 Control Bits

CSP2

CSP1

CSP0

Cyclic Sense Timing (ms)

Parameter

Cyclic Sense/FWU Timing 1

Cyclic Sense/FWU Timing 2

Cyclic Sense/FWU Timing 3

Cyclic Sense/FWU Timing 4

Cyclic Sense/FWU Timing 5

100

Cyclic Sense/FWU Timing 6

200

Cyclic Sense/FWU Timing 7

400

Cyclic Sense/FWU Timing 8

Cyclic Sense Timing, Off Time

Cyclic Sense on Time

HS1

Sample

10 µs

HS1 OFF

HS1 ON

Lx Sampling Point

Table 28. LPC Register

LPC

$110B

LX2HS1

FWU

—

HS1AUTO

—

Reset Value

—

Reset Condition

POR, NR2R

N2R,STB2RSTO2R

POR, NR2R

N2R,STB2RSTO2R

—

POR, NR2R

N2R,STB2RSTO2R

Table 29. LX2HS1 Control Bits

LX2HS1

Wake-Up Inputs Supplied by HS1

Yes, Lx Inputs Sensed at Sampling Point

Table 30. HS1AUTO Control Bits

HS1AUTO

Auto Timing HS1 in Sleep and Stop Modes

OFF

ON, HS1 Cyclic, Period Defined in TIM2 Register

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