LPC55S2X datasheet(48/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

• Supports NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1 (RSA-4096)

• Supports setting a sealed part to Fault Analysis mode through Debug authentication.

The on-chip ROM supports the following secure boot features:

• Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature verification

• Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent)

• Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent)

• Uses x509 certificate format to validate image public keys

• Supports up to four revocable Root of Trust (or Certificate Authority) keys, Root of Trust (RoT) establishment

by storing the SHA-256 hash digest of the hashes of four RoT public keys in protected flash region (PFR)

• Supports anti-rollback feature using image key revocation and supports up to 16 Image key certificates

revocations using Serial Number field in x509 certificate.

7.10 Protected Flash Region (PFR)

The protected flash region is available to configure secure boot, debug authentication, read UUID, store PUF in

key store area, and user defined fields available for specific data storage.

7.11 Memory mapping

7.12 AHB multilayer matrix

The LPC55S2x/LPC552x uses a multi-layer AHB matrix to connect the CPU buses and other bus masters

to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different

slave ports of the matrix to be accessed simultaneously by different bus masters. The device block diagram in

Figure 5 shows details of the available matrix connections.

7.13 Memory Protection Unit (MPU)

CPU has a memory protection unit (MPU) that provides fine grain memory control, enabling applications to

implement security privilege levels, separating code, data and stack on a task-by-task basis. Such requirements

are critical in many embedded applications.

The MPU register interface is located on the CPU private peripheral bus and is described in detail in Ref 1

"Cortex-M33 DEBUG"

7.14 Links to specific memory map descriptions and tables:

• Section 7.15

• Section 7.16

• Section 7.17

7.15 Memory map overview

Table 5 gives a more detailed memory map as seen by the Cortex-M33. The purpose of the four address

spaces for the shared RAMs is outlined at the beginning of this chapter. The details of which shared RAM

regions are on which AHB matrix slave ports can be seen here.

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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