LPC55S2X datasheet(71/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

[3]

VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.

[4]

An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated

voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the

reliability of the device and reduces its lifetime.

[5]

It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[6]

Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

9 Thermal characteristics

The average chip junction temperature, Tj (°C), can be calculated using the following equation:

(1)

• Tamb = ambient temperature (°C),

• Rth(j-a) = the package junction-to-ambient thermal resistance (°C/W)

• PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often

small and many times can be negligible. However it can be significant in some applications.

Symbol

Parameter

Conditions

Max/Min

Unit

HLQFP100 Package

Rth(j-a)

thermal resistance from junction to

ambient [1]

JESD51-9, 2s2p[2]

°C/W

Rth(j-c)

thermal resistance from junction to

case [3]

JESD51-9[2]

2.0

°C/W

VFBGA98 Package

Rth(j-a)

thermal resistance from junction to

ambient [1]

JESD51-9, 2s2p[2]

°C/W

Rth(j-c)

Junction-to-Top of Package Thermal

Characterization Parameter [3]

JESD51-9[2]

0.7

°C/W

HTQFP 64 Package

Rth(j-a)

thermal resistance from junction to

ambient [1]

JESD51-9, 2s2p[2]

°C/W

Rth(j-c)

thermal resistance from junction to

case [3]

JESD51-9[2]

0.3

°C/W

Table 11. Thermal resistance

[1]

Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal

performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an

application-specific environment

[2]

Thermal test board meets JEDEC specification for this package (JESD51-9).

[3]

Junction-to-Case thermal resistance determined using an isothermal cold plate. Case is defined as the bottom of the packages (exposed pad)

Symbol

Parameter

Conditions

Max

Unit

Tjmax (Device)

maximum junction temperature for

Device

Device operating per datasheet spec

+ 107

°C

Tjmax (Silicon Process) maximum junction temperature for

Silicon Process

Device operating, datasheet specifications

not guaranteed

+ 125

°C

Table 12. Maximum Junction Temperature

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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