LPC55S2X datasheet(73/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

Tamb = 25°C, VBAT_PMU = VBAT_DCDC = VDD = 3.0 V

Parameter

Conditions

Typ [2]

Unit

CCLK = 12 MHz; 2 system clock flash

access time.

CCLK = 48 MHz, 5 system clock flash

access time.

[3][4][6]

3.0

(Iterations/s) / MHz

CCLK = 60 MHz, 6 system clock flash

access time.

[3][4][6]

2.5

(Iterations/s) / MHz

CCLK = 96 MHz, 8 system clock flash

access time.

[3][4][6]

2.3

(Iterations/s) / MHz

CCLK = 100 MHz, 8 system clock flash

access time.

[4][6][5]

2.3

(Iterations/s) / MHz

CCLK = 150 MHz, 12 system clock flash

access time.

[4][6][5]

2.0

(Iterations/s) / MHz

Table 14. CoreMark score [1]...continued

[1]

Power library in SDK sets the DCDC output based on the frequency selected. For frequencies 100 MHz or below, DCDC output is set between 1.0 V to

1.075 V, for frequencies between 101 MHz to 130 MHz, DCDC output is set between 1.025 V to 1.150 V and for frequencies above 130 MHz, DCDC

output is set between 1.050 V to 1.2 V. The typical default DCDC output is 1.0 V.

[2]

Characterized through bench measurements using typical samples.

[3]

Clock source FRO. PLL disabled

[4]

Compiler settings: Keil v.5.28, optimization level 3, optimized for time on.

[5]

PLL enabled

[6]

See the FLASHCFG register in the LPC55S2x/LPC552x User Manual for system clock flash access time settings. Power Library in SDK sets the flash

wait states based on the frequency selected.

10.3 Power consumption

Tamb = -40 °C to +105 °C, unless otherwise specified. VBAT_PMU = VBAT_DCDC = VDD = 3.0 V

Symbol

Parameter

Conditions

Min

Typ[2]

Max

Unit

ARM Cortex-M33 in active mode

CoreMark code executed from

SRAMX; flash powered down

CCLK = 12 MHz

[3][4]

0.9

CCLK = 48 MHz

[3][4]

2.1

CCLK = 60 MHz

[3][4]

2.3

CCLK = 96 MHz

[3][4]

3.4

CCLK = 100 MHz

[4][5]

3.5

IDD

supply current

CCLK = 150 MHz

[4][5]

6.2

CoreMark code executed from flash;

CCLK = 12 MHz; 2 system clock

flash access time.

[3][4][6]

0.95

CCLK = 48 MHz, 5 system clock

flash access time.

[3][4][6]

2.4

CCLK = 60 MHz, 6 system clock

flash access time.

[3][4][6]

2.6

IDD

supply current

CCLK = 96 MHz, 8 system clock

flash access time.

[3][4][6]

3.4

Table 15. Static characteristics: Power consumption in active mode [1]

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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