LPC55S2X datasheet(52/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

Internal low power oscillator (FRO 1 MHz). The FRO is trimmed to +/- 15% accuracy over the entire voltage

and temperature range.

• Crystal oscillator with an operating frequency of 16 MHz to 32 MHz. Option for external clock input (bypass

mode) for clock frequencies of up to 25 MHz.

Crystal oscillator with 32.768 KHz operating frequency. Option for external clock input (bypass mode) for clock

frequencies of up to 100 kHz.

• Each crystal oscillator has one embedded capacitor bank which can be used as an integrated load capacitor.

Using APIs, the capacitor banks on each crystal pin can tune the frequency for crystals with a Capacitive Load

(CL) which conserves board space and reduces costs.

7.19.2 PLL (PLL0 and PLL1)

PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the need for a high-frequency

external clock. PLL0 and PLL1 can run from the internal FRO 12 MHz output, the external oscillator, internal

FRO 1 MHz output, or the 32.768 KHz RTC oscillator.

The system PLL accepts an input clock frequency in the range of 2 kHz - 150 MHz. The input frequency is

multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The PLL can be enabled or

disabled by software.

7.19.3 Clock generation

The system control block facilitates the clock generation. Many clocking variations are possible. Figure 7 gives

an overview of potential clock options. Table 9 describes signals on the clocking diagram. The maximum clock

frequency is 150 MHz.

Remark: The indicated clock multiplexers shown in Figure 7 are synchronized. In order to operate, the currently

selected clock must be running, and the clock to be switched to must also be running. This is so that the

multiplexer can gracefully switch between the two clocks without glitches. Other clock multiplexers are not

synchronized. The output divider can be stopped and restarted gracefully during switching if a glitch-free output

is needed.

The low-power oscillator provides a frequency in the range of 1 MHz. The accuracy of this clock is limited to

+/- 15% over temperature, voltage, and silicon processing variations after trimming made during assembly. To

determine the actual watchdog oscillator output, use the frequency measure block.

The part contains one system PLL that can be configured to use a number of clock inputs and produce an

output clock in the range of 1.2 MHz up to the maximum chip frequency, and can be used to run most on-chip

functions. The output of the PLL can be monitored through the CLKOUT pin.

Name

Description

32k_osc The 32 kHz output of the RTC oscillator. The 32 kHz clock must be enabled in the RTCOSCCTRL register.

clk_in

This is the internal clock that comes from the external oscillator.

frg_clk

The output of each Fractional Rate Generator to Flexcomm clock. Each FRG and its source selection is shown

in Figure 7.

fro_12m 12 MHz divided down from the currently selected on-chip FRO oscillator.

fro_hf

The currently selected FRO high speed output at 96 MHz.

main_clk The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source

selection are shown in Figure 7.

mclk_in The MCLK input function, when it is connected to a pin by selecting it in the IOCON block.

pll0_clk The output of the PLL0. The PLL0 and its source selection is shown in Figure 7.

Table 9. Clocking diagram signal name descriptions

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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