LPC55S2X datasheet(75/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

Tamb = -40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[2]

Typ[3] Max

Unit

CCLK = 96 MHz; 8 system clock

flash access time, Tamb = 85°C

[4][5][6]

4.1

CCLK = 96 MHz; 8 system clock

flash access time, Tamb = 105°C [4][5][6]

4.8

7.6

Table 16. Static characteristics: Power consumption in active mode [1]...continued

[1]

For device revision 1B, power library in SDK sets the DCDC output based on the frequency selected. For frequencies 100 MHz or below, DCDC output

is set between 1.0 V to 1.075 V. Frequencies between 101 MHz to 130 MHz, DCDC output is set between 1.025 V to 1.150 V, and for frequencies above

130 MHz, DCDC output is set between 1.050 V to 1.2 V. For device revision 0A, the default typical DCDC output is 1.1 V and for device revision 1B, the

typical default DCDC output is 1.0 V.

[2]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). Characterized through bench measurements using typical

samples.

[3]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C). Characterized through bench measurements using typical

samples. VBAT_PMU = VBAT_DCDC = VDD = 1.8 V

[4]

Clock source FRO. PLL disabled

[5]

Compiler settings: IAR v.8.20.2., optimization level 0, optimized for time off.

[6]

See the FLASHCFG register in the LPC55S2x/LPC552x User Manual for system clock flash access time settings. Power Library in SDK sets the flash

wait states based on the frequency selected.

Tamb = -40 °C to +105 °C, unless otherwise specified. VBAT_PMU = VBAT_DCDC = VDD = 3.0 V

Symbol

Parameter

Conditions

Min

Typ[2]

Max

Unit

ARM Cortex-M33 in active mode

IDD

supply current

CoreMark code executed from

SRAMX; flash powered down

CCLK = 1 MHz, Tamb = 25 °C

[3][4]

0.8

CCLK = 16 MHz, Tamb = 25 °C

[4][5]

1.1

IDD

supply current

CoreMark code executed from flash;

CCLK = 1 MHz, 1 system clock

flash access time, Tamb = 25 °C

[3][4][6]

0.9

CCLK = 12 MHz, 2 system clock

flash access time, Tamb = 25 °C

[4][5][6]

1.2

Table 17. Static characteristics: Power consumption in active mode [1]

[1]

For device revision 1B, power library in SDK sets the DCDC output based on the frequency selected. For frequencies 100 MHz or below, DCDC output

is set between 1.0 V to 1.075 V. Frequencies between 101 MHz to 130 MHz, DCDC output is set between 1.025 V to 1.150 V, and for frequencies above

130 MHz, DCDC output is set between 1.050 V to 1.2 V. For device revision 0A, the default typical DCDC output is 1.1 V and for device revision 1B, the

typical default DCDC output is 1.0 V.

[2]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C). Characterized through bench measurements using typical

samples.

[3]

Clock source FRO. System Oscillator disabled. PLL disabled

[4]

Compiler settings: IAR v.8.20.2., optimization level 0, optimized for time off.

[5]

System Oscillator enabled. FRO disabled. PLL disabled.

[6]

See the FLASHCFG register in the LPC55S6x/LPC55S2x User Manual for system clock flash access time settings. Power Library in SDK sets the flash

wait states based on the frequency selected.

Tamb = -40 °C to +105 °C, unless otherwise specified. VBAT_PMU = VBAT_DCDC = VDD = 3.0 V

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

ARM Cortex-M33 in sleep mode

IDD

supply current

CCLK = 12 MHz, PLL disabled

[2][3]

0.7

Table 18. Static characteristics: Power consumption in sleep mode

LPC55S2X_LPC552X

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Data sheet

Rev. 2.3 — 29 August 2024

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