LPC55S2X datasheet(61/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

• Sampling frequencies supported depends on the specific device configuration and applications constraints

(For example, system clock frequency and PLL availability) but generally supports standard audio data rates.

7.23.4 High-speed SPI serial I/O controller

7.23.4.1 Features

• Master and slave operation.

• The maximum supported bit rate for SPI master mode (transmit/receive) and slave mode (transmit/receive) is

50 Mbit/s.

• Data frames of 4 to 16 bits supported directly. Larger frames supported by software.

• The SPI function supports separate transmit and receive FIFOs with eight entries each.

• Supports DMA transfers: SPIn transmit and receive functions can operated with the system DMA controller.

• Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up

an SPI memory.

• Up to Four Slave Select input/outputs with selectable polarity and flexible usage.

7.24 SDIO/MMC interface

Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. SDIO with support for up to

two cards. Supported card types are MMC, SDIO, and CE-ATA. Supports SD2.0, and SDR25 (52MHz).

7.24.1 Features

• Secure Digital memory protocol commands.

• Secure Digital I/O protocol commands.

• Multimedia Card protocol commands.

• CE-ATA digital protocol commands.

• Two SD or MMC (4.4), CE-ATA (1.1), or eMMC (4.4) device.

• CRC 2.0 generation and error detection.

• SDIO interrupts in 1-bit and 4-bit modes.

• Block size of 1 to 65,535 bytes.

• Internal (bus mastering) DMA.

• Two FIFOs, TX and RX FIFO (FIFO depth = 32 and FIFO data width = 32 bits).

7.25 Standard counter/timers (CT32B0 to 4)

The LPC55S2x/LPC552x includes five general-purpose 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can

optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values,

based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when

an input signal transitions, optionally generating an interrupt.

7.25.1 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal

transitions. A capture event may also generate an interrupt.

LPC55S2X_LPC552X

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Data sheet

Rev. 2.3 — 29 August 2024

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