RC9624DP datasheet(11/34 Pages) ETC2

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2-1

D96V24DSA

2.0

2.0 Hardware Interface

The modem functional hardware interface signals are shown in Figure 2-1. In this

diagram, any point that is active low is represented by a small circle at the signal

point.

Edge triggered inputs are denoted by a small triangle (e.g., TDCLK). Open-

Collector (open-source or open-drain) outputs are denoted by a small half-circle

(e.g., IRQ). Active low signals are overscored (e.g., POR).

A dock intended to activate logic on its rising edge (low-to-high transition) is

called active low (e.g., RDCLK), while a clock Intended to activate logic on its

falling edge (high-to-low transition) is called active high (e.g., TDCLK). When a

clock input is associated with a small circle, the input activates on a falling edge.

If no circle is shown, the input activates on a rising edge.

The modem pin assignments are shown in Figure 2-2. The pin assignments are

listed by pin number in Table 2-1.

The hardware interface signal functions are summarized by major interface in

Table 2-2.

The digital and analog interface characteristics are defined in Table 2-3 and

Table 2-4, respectively.

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