1.0 Functional Description
RC96V24DP
1.2 Technical Specifications
Single Device Data/Modem Data Pump
1-2
D96V24DSA
1.2.4 Tone Detection
Answer Tone and Call Progress Tones:
Tones can be detected as follows:
•
Call progress frequency range: 340 ±5 Hz to 640 ±5HZ
•
Answer tone frequency ranges: CCITT (2100 ±15Hz), Bell (2225 ±10 Hz),
or Bell FSK originate tone (1270 ±10 Hz)
•
Detection range: -9 dBm to -43 dBm
•
Default detection threshold: -43 dBm
•
Response time: 75 ±2 ms
•
The passband and tone detect threshold can be changed in DSP RAM.
V.23 and V21 Tones:
Tones can be detected as follows:
•
V.23 forward channel mark: 1300 ±10 Hz
•
V.23 backward channel mark: 390 ±10 Hz
•
V.21 high band mark (1650 ±10 Hz) or low band mark (980 ±10 Hz)
•
Detection range: -9 dBm to -43 dBm
•
Default detection threshold: -43 dBm
•
Response time: 25 ± 2 ms
The passbands and tone detect thresholds can also be changed in the DSP
RAM.
1.2.4.1 DTMF Detection
The modem can detect a valid DTMF tone pair (indicated by DTDET) and load a
corresponding hexadecimal code into the modem interface memory (DTDIG).
1.2.4.2 Equalizers
Equalization functions are incorporated that improve performance when
operating over low quality lines.
Automatic Adaptive Equalizer.
An automatic adaptive equalizer in the receiver
compensates for transmission line amplitude and group delay distortion.
Updating of the taps can be enabled or disabled (EQFZ bit). The equalizer taps
can also be reset (EQRES bit).
Fixed Compromise Equalizers.
Fixed compromise equalizers are provided in
the transmitter and receiver. The equalizers are programmable in DSP RAM.
1.2.4.3 Transmit Level
The transmitter output level is -10 dBm ±1 dB using the internal hybrid circuit.
The attentuation is selectable from 0 dBm to -15 dBm in 1 dB steps (TLVL bits).
1.2.4.4 Transmit Timing
Transmitter timing is selectable between internal (±0.01%), external, or loopback
(TXCLK bits). When external clock is selected, the external clock rate must equal
the desired data rate ±0.01% with a duty cycle of 50 ±20%.
1.2.4.5 Scrambler/
Descrambler
The modem incorporates a self-synchronizing scrambler/descrambler satisfying
the applicable CCITT or Bell requirement. The scrambler and descrambler can be
enabled or disabled (SDIS and DDIS bits, respectively).
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