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AK4635 Datasheet(PDF) 17 Page - Asahi Kasei Microsystems |
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AK4635 Datasheet(HTML) 17 Page - Asahi Kasei Microsystems |
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17 / 81 page ![]() [AK4635] Rev. 0.6 2007/10 - 17 - ■ Timing Diagram FCK 1/fCLK MCKI tCLKH tCLKL VIH VIL 1/fMCK MCKO tMCKOH tMCKOL 50%DVDD 1/fFCK dFCK dFCK 50%DVDD dMCK = tMCKOL x fMCK x 100% Figure 6. Clock Timing (PLL/EXT Master mode) (MCKO is not available at EXT Master Mode) FCK BICK 50%DVDD SDTO 50%DVDD tBSD tSDS SDTI VIL tSDH VIH dBCK tDBF 50%DVDD tBCK MSB MSB BICK 50%DVDD (BCKP = "0") (BCKP = "1") Figure 7. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”) |
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