MPC8280 datasheet(336/1386 Pages) FREESCALE

336 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-28

Freescale Semiconductor

0x10458

Outbound message register 0 (OMR0)

R/W

undefined

9.12.1.2/9-67

0x1045C

Outbound message register 1 (OMR1)

R/W

undefined

9.12.1.2/9-67

0x10460

Outbound doorbell register (ODR)

R/W

0x0000_0000

9.12.2.1/9-68

0x10468

Inbound doorbell register (IDR)

R/W

0x0000_0000

9.12.2.2/9-69

0x10480

Inbound message interrupt status register (IMISR)

R/W

0x0000_0000

9.12.3.4.5/9-82

0x10484

Inbound message interrupt mask register (IMIMR)

R/W

0x0000_0000

9.12.3.4.6/9-83

0x104A0

Inbound free_FIFO head pointer register (IFHPR)

R/W

0x0000_0000

9.12.3.2.1/9-72

0x104A8

Inbound free_FIFO tail pointer register (IFTPR)

R/W

0x0000_0000 9.12.3.2.1/9-72

0x104B0

Inbound post_FIFO head pointer register (IPHPR)

R/W

0x0000_0000

9.12.3.2.2/9-73

0x104B8

Inbound post_FIFO tail pointer register (IPTPR)

R/W

0x0000_0000

9.12.3.2.2/9-73

0x104C0

Outbound free_FIFO head pointer register (OFHPR)

R/W

0x0000_0000

9.12.3.3.1/9-75

0x104C8

Outbound free_FIFO tail pointer register (OFTPR)

R/W

0x0000_0000 9.12.3.3.1/9-75

0x104D0

Outbound post_FIFO head pointer register (OPHPR)

R/W

0x0000_0000

9.12.3.3.2/9-76

0x104D8

Outbound post_FIFO tail pointer register (OPTPR)

R/W

0x0000_0000

9.12.3.3.2/9-76

0x104E4

Message unit control register (MUCR)

R/W

0x0000_0002 9.12.3.4.7/9-84

0x104F0

Queue base address register (QBAR)

R/W

0x0000_0000 9.12.3.4.8/9-85

0x10500

DMA 0 mode register (DMAMR0)

R/W

0x0000_0000

9.13.1.6.1/9-89

0x10504

DMA 0 status register (DMASR0)

R/W

0x0000_0000

9.13.1.6.2/9-91

0x10508

DMA 0 current descriptor address register (DMACDAR0)

R/W

0x0000_0000

9.13.1.6.3/9-92

0x10510

DMA 0 source address register (DMASAR0)

R/W

0x0000_0000

9.13.1.6.4/9-93

0x10518

DMA 0 destination address register (DMADAR0)

R/W

0x0000_0000

9.13.1.6.5/9-94

0x10520

DMA 0 byte count register (DMABCR0)

R/W

0x0000_0000

9.13.1.6.6/9-94

0x10524

DMA 0 next descriptor address register (DMANDAR0)

R/W

0x0000_0000

9.13.1.6.7/9-95

0x10580

DMA 1 mode register (DMAMR1)

R/W

0x0000_0000

9.13.1.6.1/9-89

0x10584

DMA 1 status register (DMASR1)

R/W

0x0000_0000

9.13.1.6.2/9-91

0x10588

DMA 1 current descriptor address register (DMACDAR1)

R/W

0x0000_0000

9.13.1.6.3/9-92

0x10590

DMA 1 source address register (DMASAR1)

R/W

0x0000_0000

9.13.1.6.4/9-93

0x10598

DMA 1 destination address register (DMADAR1)

R/W

0x0000_0000

9.13.1.6.5/9-94

0x105A0

DMA 1 byte count register (DMABCR1)

R/W

0x0000_0000 9.13.1.6.6/9-94

0x105A4

DMA 1 next descriptor address register (DMANDAR1)

R/W

0x0000_0000

9.13.1.6.7/9-95

0x10600

DMA 2 mode register (DMAMR2)

R/W

0x0000_0000

9.13.1.6.1/9-89

0x10604

DMA 2 status register (DMASR2)

R/W

0x0000_0000

9.13.1.6.2/9-91

Table 9-3. Internal Memory Map (continued)

Address

(offset)

Access

Reset

Section/Page

MPC8280 Datasheet(PDF) 336 Page - Freescale Semiconductor, Inc

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